AMD has announced a major investment exceeding $10 billion in Taiwan, aimed at enhancing the production capabilities of AI chips and servers. This initiative highlights the ongoing demand for advanced computing resources as companies ramp up their AI infrastructure. With industry leaders like Google and Meta making substantial investments in AI, AMD's move aligns with a trend where hyperscalers are expected to spend up to $700 billion on data centers by 2026, according to a recent McKinsey report.
As part of this initiative, AMD will begin production of its sixth-generation EPYC CPUs, codenamed Venice, using TSMC's advanced 2-nm technology. This development is significant for the semiconductor industry, as Venice will be the first high-performance computing (HPC) product to enter production at this advanced node. AMD's CEO, Lisa Su, underscored the importance of this milestone, stating, "As AI adoption accelerates, our global customers are rapidly scaling AI infrastructure to meet growing compute demand." This investment not only strengthens AMD's HPC capabilities but also aligns with Taiwan's semiconductor ecosystem, enhancing collaboration with global partners.
However, the semiconductor industry is grappling with considerable challenges. TSMC, the world's leading chip foundry, is struggling to keep up with the surging demand for AI chips, which has exceeded earlier production forecasts. Total chip production is projected to reach $1 trillion by 2030. TSMC plans to invest nearly $56 billion this year to increase its production capacity, yet it admits that it may not meet customer demand until at least 2027. Dan Hutcheson, vice chair of TechInsights, noted that supply chain constraints are hindering TSMC’s ability to scale production effectively, compounded by limitations from equipment suppliers.
AMD is not alone in tackling these challenges. Similar to NVIDIA, which has made substantial investments in the AI ecosystem, AMD is collaborating with strategic partners to advance silicon technologies and improve manufacturing capabilities. Notably, AMD is working with Taiwan-based chip packagers ASE and SPIL to develop next-generation wafer-based 2.5D bridge interconnect technology, which aims to enhance computing efficiency and power management in the Venice CPUs.
This collaboration seeks to enable the deployment of more efficient AI systems. ASE's senior vice president, Steven Tsai, remarked that their partnership represents a significant step forward in scaling advanced packaging technologies. As demand for AI chips surges, traditional packaging firms like ASE are expanding their operations to meet the requirements of a rapidly changing market.
AMD’s investment strategy aims to result in faster and more efficient systems that deliver superior performance within practical power constraints. The company recently marked a milestone in its partnership with Powertech Technology by qualifying the industry's first 2.5D panel-based EFB interconnect technology, which supports high-bandwidth interconnects at scale. This advancement is particularly noteworthy as the surface area of AI chips increases beyond conventional sizes, leading to a shift towards wafer-level packaging solutions.
Looking ahead, AMD and its partners are preparing for the deployment of the AMD Helios rack-scale platform in the latter half of 2026. This platform represents a significant advancement toward establishing production-ready AI infrastructure, supported by AMD’s Instinct MI450X GPUs, EPYC CPUs, and advanced networking solutions. Key manufacturing partners, including Sanmina in California and several Taiwanese firms, are key in building these systems, underscoring AMD's commitment to driving innovation in AI infrastructure.
AMD's investment in Taiwan is a strategic response to the rising demand for AI computing power. As the AI field continues to evolve, the company is positioned to use its partnerships and technological advancements to address the challenges ahead, contributing to a more integrated and efficient AI ecosystem.
